Annular ring

How do we state the minimum annular ring? Do we need an additional tag for it in the holes element section? 

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  • Yes, we will need the minimum designed annular ring to determine if a supplier have capability to meet IPC class 2 or 3 or even tighter like we could have in IPC  addendum standards.

    The required minimum annular ring allowed on the finished PCB will always be set by standard - IPC class 2 or 3  - or Customer profile could require e.g. "tangency" - hole ring can be tangent to pad outline.

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  • Jan Pedersen OK - Since we haven't released version 1 yet, I'll add a minimum_designed_annular_ring tag, under the holes element.

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  • I would suggest that we also add "Acceptable Minimum Annular ring".   Description: The minimum acceptable annular ring on the finished PCB. 

    Requirement:  "according to Specified Acceptability Standard."   If nothing is specified the default requirement is IPC Class 2.

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  • I find also useful to have an extra "modify_via_diameter_allowed" tag, as manufacturers often have the possibility to meet the annular ring specifications after such modifications. 

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  • I like this, but I have never seen it used ;) . Can others comment on this please? If we ad this, should we also add a restriction: "modify_via_diameter_accepted on approval" . Maybe not perfect text - my meaning is: it must be approved before production.

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  • Athanasios Kallinis Would you place "modify_via_diameter_allowed" as a boolean under the "allowed_modifications" element? Or under "holes"?

    Jan Pedersen  Wouldn't anything that requires an approval be the default behaviour? If "modify_via_diameter_allowed" is "true" you are allowed to change,  if "false" or not set you are not.

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  • Andreas Lydersen that is a really good question.

    In the "holes" list, that would be as clear as it gets, but it would require more care and accuracy, as there could be many different via types to specify.  If placed under  "allowed_modifications" it is less likely to be missed/forgotten, but would still require additional documentation if vias with different specification/function should be excluded from the modification (this leads to double presence in both places).

    Keeping in mind that reducing the EQs and time loss in the supply chain is a main target, I tend to think that placement unter "holes" combined with sensible use of the feature only for the critical vias (where usually no modifications are allowed) would be the way to go.

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  • I  ve moved this in under the Ideas section so that it can be planned and executed upon.

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  • Added in https://github.com/CircuitData/CircuitData-Language/pull/9. Waiting for approval from the board.

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